1. Field of the Invention
The present invention relates to an insulated gate type field effect transistor which is used as a power switching element for a motor driving inverter, an igniter or the like.
2. Related Arts
There has been well known a bipolar integrated circuit in which an embedded region is provided in a semiconductor layer to reduce a collector resistance of a bipolar transistor. A thermal diffusion method is generally used to form such an embedded region. In this method, an oxide film is used as a mask and impurities are diffused through a diffusion window which is formed in the oxide film by partially opening the oxide film. For example, when arsenic (As) is diffused by using a solid source As.sub.2 O.sub.3, the solid source As.sub.2 O.sub.3 is vaporized, and then supplied to the diffusion window under carrier gas to diffuse As into the semiconductor layer.
In this case, oxidizing gas is used as the carrier gas, and therefore a thin oxide film is grown on the surface of the semiconductor layer which is exposed to the outside through the diffusion window. That is, a recess is formed on the surface of the underlying silicon layer through formation of the oxide film during the diffusion process. The same phenomenon occurs in case of diffusing other impurities (phosphorus P, antimony Sb, boron B, etc.).
Generally, a silicon layer is then formed at a predetermined thickness by an epitaxial growth method after the mask and the grown oxide film are removed. In this process, a recess is also formed in succession on the surface of the grown silicon layer, and thus the surface of the silicon layer becomes uneven (that is, a step portion is formed on the silicon layer).
The step portion due to the unevenness of the silicon layer is used to position a pattern of the embedded region and a surface pattern (to form elements) in a process of forming a bipolar integrated circuit.
A structure having an embedded region is also known in a vertical type IGBT (insulated gate bipolar transistor) and a vertical type MOSFET (as disclosed in WO91/03842, Japanese Examined Patent Publication No. Hei3-30310).